UltraSoC’s announcement of a hardware-basedlockstep solution for automotive applications being a good example. RISC-V lacks native support for lockstep, which is strongly recommended for designs with a functional safety dimension. Meanwhile at the conference, our CTO Gajinder Panesar continued to encourage ecosystem members to take a more system-level approach, as well as pushing forward the ISA and core design dimensions. Gadge argues that RISC-V will take its place alongside a raft of other processor architectures – most notably Arm. So developing an ecosystem that can support heterogeneous designs – those that include cores built with different base architectures – is vital. To read more, please visit: https://www.ultrasoc.com/risc-v-summit_automotive_system-level-design_wd-swerv-core/ ]]>