NXP chip which combines an ARM Cortex-M0 and Cortex-M4. The real trick is the RI5CY and Zero-RI5CY chips on the VEGAboard, a four-stage RISC-V RV32IMCCXpulp CPU, which come from a PULP platform with a parallel platform for various processing needs. In short, with the VEGAboard, you’re not running a blink() sketch on the RISC-V microcontroller but on the ARM microcontrollers, while using the RISC-V chip to read accelerometers and toggle pins. It’s a coprocessor, but it’s RISC-V. To read more, please visit: https://hackaday.com/2019/02/04/openisa-launches-free-risc-v-vegaboard/.]]>