ETH Zurich offers a good opportunity to take a closer look at RISC-V and get to know the experts. After all, the ETH with the Institute for Integrated Systems – especially the Department of Digital Circuits and Systems and Prof. Luca Benini – is an important development site for RISC-V processors. The PULP processor platform developed here (PULP: Parallel Ultra Low Power) was designed as a cluster – with many small energy-efficient RISC-V cores. To read more, please visit: https://www.elektroniknet.de/elektronik/halbleiter/risc-v-workshop-an-der-eth-zuerich-165234.html. Please note that the original article is in German.]]>