Skip to main content
search
Ecosystem News

Video: #CSWSpring21 / RISC-V for acceleration of data-parallel workloads: from IoT to HPC

Video: #CSWSpring21 / RISC-V for acceleration of data-parallel workloads: from IoT to HPC
In this talk by Luca Benini (University of Bologna / ETH Zurich), we will look into RISC-V based architectures for acceleration of data-parallel workloads. The focus will be on how we can exploit the flexibility of the ISA and the freedom it gives in architectural design to create efficient but flexible accelerators for a range of applications, from the IoT to the datacenter.

Subscribe for updates, event info, webinars, and the latest community news

About
Technical Steering Committee
Board of Directors
FAQ
Contact Us
About RISC-V
History of RISC-V
Blog
News
Announcements
Policies
Privacy Policy
Code of Conduct
Antitrust Policy
Brand Guidelines
Specification
Ratified
Under Development
Contribute
Developers
Get Started
Training
Development Partners
Developer Boards
Labs
Mentorship
Technical Wiki
Industries
Automotive
Artificial Intelligence
Case Studies
Exchange
Landscape
Software Ecosystem Dashboard
Events
RISC-V Summit
Calendar
Videos
Community Meetings
Members
Current Members
Resources
Recognition
Resources
Get RISC-V Gear
Join RISC-V International
Becoming a member of RISC-V International allows companies and individuals to actively influence the development of an open, royalty-free instruction set architecture, driving innovation in custom processor designs.
JOIN NOW