RISC-V Researchers publish new RISC-V SoC | Robin Mitchell, Electropages

As RISC-V continues to increase in popularity, more architecture implementations are being developed, and one research team has demonstrated a 3-stage pipeline RISC-V SoC with various peripherals. What advantages does RISC-V present as a future CPU architecture, what did the researchers design, and could FPGAs play a key role in RISC-V development?

Read the full article.