Imagine a rocket, meticulously engineered for efficiency, speed and reliability, ready to launch into the vast expanse of space. The Mi-V RV32 v4.0 soft RISC-V processor is much like that rocket, designed to propel embedded systems to new performance levels within our Field-Programmable Gate Array (FPGA) ecosystem. Just as a rocket adapts to varying payloads and missions, this processor’s configurability makes it a versatile powerhouse for applications from general-purpose to high-reliability real-time tasks.
In this blog post, we’ll dive into the upcoming Mi-V RV32 v4.0, a 32-bit soft RISC-V processor launching in 2025. You’ll discover its key enhancements, including speed boosts, resource-efficient options and advanced safety features. We’ll explore its context within the RISC-V ecosystem, break down its major features and guide you on how to leverage this IP for your next project with Microchip’s RT PolarFire®, RTG4, PolarFire and Igloo2 FPGAs.
The RISC-V architecture has transformed the semiconductor industry with its open-standard instruction set, enabling customizable and cost-effective processors. Since its debut in 2020, the Mi-V RV32 IP has been a cornerstone for our FPGA users, evolving through customer feedback and technological advancements. The upcoming v4.0 release reflects our commitment to pushing boundaries, integrating lessons from previous iterations to meet diverse application needs. As embedded systems demand higher performance and reliability, the Mi-V RV32 v4.0 is poised to lead in 2025, aligning with trends toward modular, scalable processor designs.
A block diagram of the upcoming Mi-V RV32 v4.0 processor IP is illustrated below. The core consists of a single order RISC-V 32-bit HART (HARdware Thread). V4.0 will add support for Atomic Memory Operations (AMO) in addition to the existing IMFC extensions. The HART has a dedicated Sub System featuring Caches and Tightly Coupled Memory (TCM) options as well as a range of integrated peripherals and AMBA Interfaces.