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HiPEAC 2025

January 21, 2025 @ 10:00 am - 5:00 pm

RISC-V: the cornerstone ISA for the next generation of HPC infrastructures

RISC-V is unique, even revolutionary, because it is a free, open-source ISA to which software can be ported, hardware can be developed, and new solutions can be built without the cost of licensing proprietary ISAs and/or paying royalties. The current rise of RISC-V coincides with the slowing of Moore’s Law, meaning that increases in total processing power no longer comes along with new fabrication technologies, with the explosive growth in machine learning and AI applications, demanding massive increases in processing power, and with the growing availability in the market of chips designed by different vendors.

There are currently many RISC-V based hardware products from different companies, and there are a variety of off-the-shelf, low-cost development boards as well as boards suitable for compute-intensive applications running standard Linux. The freedom to configure and customize the RISC-V ISA in accordance with the applications’ needs, including custom instructions, is one of its strongest appeals of RISC-V for compute-intensive applications, making the RISC-V ISA an attractive choice for an unprecedented number of use cases in HPC and AI, IoT, Virtual/Augmented Reality. The future will see an explosion of applications that are designed for RISC-V.

After the large interest generated by the 2024 edition, in this new edition of the workshop we will discuss the improvement that took place in the last year, regarding the novel hardware availability, the presence of new features and current software stack progress.

The workshop will bring together researchers from different disciplines, representatives from industries, computer architects, developers of scientific applications and users to describe the state of the art and outline the paths to be taken by RISC-V to make it the preferred ISA for HPC applications.

Contributions will address, but are not limited to, the following topics:

  • RISC-V extensions
  • System Optimizations
  • Hardware Stack
  • Co-design
  • Scalability and Reliability

The workshop will provide a lively discussion and present early experiences and use cases of HPC infrastructure powered by RISC-V platforms.

Organizers

Teresa Cervero

Daniele Gregori

 

For More Information on RISC-V Session

Details

Date:
January 21, 2025
Time:
10:00 am - 5:00 pm
Event Category:
Website:
https://www.hipeac.net/2025/barcelona/#/