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Verification Engineer 3+Yrs

Verification Engineer 3+Yrs

Website SiFive Inc

pioneers who introduced RISC-V to the world

About SiFive

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize, and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, datacenter, mobile, and consumer. With SiFive, the future of RISC-V has no limits.

Responsibilities :

  • Develop SV/UVM based testbenches for IP, sub-systems and SoC.
  • Develop IP/Unit level test-plans and develop test-cases in SV/UVM
  • Understand and develop system level use-cases/test-cases in ‘C’
  • Ensure Feature verification and coverage goals are met.
  • Work Closely with design teams in debugging and closing design issues.
  • Work with global teams across time zones.

Requirements :

  • 3-5 years of strong experience in design Verification of IP, sub-systems, SoC/ASICs
  • Strong in SystemVerilog,  UVM, C/C++.
  • Require Knowledge of hardware interfaces AXI, AHB, APB.
  • Require Experience in RISC-V ISA and ASM programming
  • Good understanding of front-end EDA tools such as VCS/Questa/Incisive simulators.
  • Should possess strong analytical, debugging skills
SiFive is proud to be an equal employment opportunity workplace. We offer a competitive compensation package; employee stock option program, and much more.

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