Verilator, an open-source Verilog emulator, is a well-established and community-supported hardware verification tool. It is widely used in developing and testing RISC-V CPU RTL designs. Rocket, CVA6, BOOM, and most other RISC-V RTL designs in the RISC-V Chipyard toolkit lean on Verilator to emulate their respective designs. A common requirement in hardware verification is the ability to access the value of hardware elements and registers during live emulation. The Verilog Procedural Interface (VPI) is an interface that enables this ability. It is defined under the IEEE 1364 and IEEE 1800 standards. Two of the functions provided by VPI are “vpi_get_value” and “vpi_put_value”, these are the sole function that allows C/C++ code to access Verilog scalars during live emulation. Currently, accessing elements within an array requires the use of iterators and consecutive calls to these functions. This poses a high-performance cost when attempting to validate the contents of large arrays. However, IEEE VPI standard does define “vpi_get_value_array” and “vpi_put_value_array” functions, which allow C/C++ code to access verilog arrys with a single call. These functions are unimplemented in the latest version of Verilator and depending on their implementation, may be used to access arrays with less memory utilization, fewer instructions, and faster emulation time.

The project I propose will ask the mentee to contribute to the Verilator codebase by implementing VPI array accessor functions and conducting a performance analysis comparing the use of the newly implemented functions versus the conventional approach in validating large Verilog arrays. The performance analysis will use CVA6 to serve as the RISC-V core RTL model for metric testing.

Repository URL: https://github.com/verilator/verilator

Expected Outcomes: Implementation of two VPI functions in Verilator, source code for a RISC-V CPU RTL emulation performance comparison, and a final report/presentation detailing the results of the comparisons. Short written progress updates as well.

Education Level: Only undergraduate experience in computer engineering and Verilog/RTL development is required. Graduate degree recipients will be overqualified.