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Electronics Weekly Article: Microsemi And Imperas Develop RISC-V ISS

By December 15, 2017May 12th, 2021No Comments

The collaboration delivers the first commercially available instruction set simulator (ISS) for Microsemi’s Mi-V ecosystem, a program designed to increase adoption of Microsemi’s RISC-V soft CPU product family utilizing RISC-V open instruction set architectures (ISAs). “The Imperas EPK allows for rapid software development and debugging of corner cases when using Mi-V soft CPUs on Microsemi field programmable gate array (FPGA) products. We look forward to working with Imperas and other Mi-V ecosystem members to deliver more RISC-V processor-based solutions,” says Microsemi’s Bruce Weyer.
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