Barron's Article: Western Dig, Nvidia On Board with ‘RISC-V,’ So Pay Attention, Says Benchmark

If you like semiconductors, you should really check out this “RISC-V” thing, according to a missive today from Gary Mobley of The Benchmark Company. RISC-V, in case you don’t know, is the latest incarnation of the “reduced instruction set computing” architecture, devised by Professor David Patterson of U.C. Berkeley about 40 years ago. I interviewed Patterson about RISC-V last summer for Barron’s print magazine. The notion is that by making the “instruction-set architecture,” or ISA, of a chip more like open source, where it can be modified, it is possible to make chips that are tailored to a given need and therefore more efficient and less costly to produce. Some of these qualities are evident in the “Tensor Processing Unit,” or TPU, which Patterson helped devise for Alphabet’s (GOOGL) Google’s machine learning efforts.
To read more, please visit: https://www.barrons.com/articles/western-dig-nvidia-on-board-with-risc-v-so-pay-attention-says-benchmark-1515001875