The open-source RISC-V processor architecture is getting a trace function through an IP (intellectual property) block from Cambridge-based UltraSoC.
It supports both 32 and 64-bit RISC-V designs, and is intended to integrate with the firms other RISC-V offerings. “The addition of trace capabilities means that UltraSoC provides the most comprehensive RISC-V commercial debug solution,” claimed the firm.
RISC-V processor vendors Andes, Codasip, Microsemi, Roa Logic, SiFive and Syntacore are backing the trace IP, according to UltraSoC.
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