SiFive Inc. And Andes Technology Corporation Join Forces To Promote RISC-V

Andes Technology Corporation, the prominent CPU IP provider, and SiFive Inc., the leading provider of ASIC design service and RISC-V CPU Core IP, have announced they are joining forces to jointly promote RISC-V. The two companies will each contribute their unique expertise in CPU development and support to expand the ecosystem for the RISC-V instruction set architecture (ISA) to enable a new era of processor innovation through open standard collaboration.
“RISC-V is providing a newfound freedom in silicon design, fostering stronger collaboration across the semiconductor industry. We’re excited to see SiFive and Andes partnering to expand the RISC-V ecosystem, making it easier for other industry players to quickly bring to market innovative designs based on the free and open RISC-V ISA,” said Rick O’Connor, Executive Director of the non-profit RISC-V Foundation.
As a founding member of the RISC-V Foundation, Andes Technology is dedicated to bringing its expertise in low-power and high performance 32/64 bit processor cores to the development of the RISC-V ISA. For example, at the recent RISC-V Workshop in Barcelona, Andes proposed an extension to the RISC-V ISA based on the DSP ISA used in Andes’ successful D10 and D15 processors. In addition, Andes debuted four new RISC-V processor IPs with compliant floating-point and Linux support: the 64-bit NX25F and AX25, and 32-bit N25F and A25.
To read more, please visit: http://www.andestech.com/news-d.php?cls=1&id=560