Bit-tech Article: SiFive's RISC-V Cores Launch In Two SSD Families

The RISC-V open instruction set architecture (ISA) has scored another pair of big wins this week, with SiFive‘s core intellectual property (IP) being picked for a pair of high-performance solid-state drive (SSD) families from Mobiveil and Fadu.
Designed to scale from low-power single-core microcontroller implementations to high-performance many-core supercomputers, the RISC-V ISA began life in 2010 at the University of California at Berkeley as a collaborative alternative to proprietary ISAs including x86, Arm, and MIPS. Since reaching a feature-complete state, interest in the ISA for commercial use has been growing: Late last year Western Digital confirmed it would launch RISC-V based data processing products at scale, Nvidia is replacing its in-house RISC-based ISA with RISC-V in its logic controllers and Rambus has launched a RISC-V based security product.
At the forefront of this is SiFive, founded by original RISC-V researchers Krste Asanović, Yunsup Lee, and Andrew Waterman and recently the recipient of investment from Intel Capital. It’s SiFive’s implementations of the RISC-V architecture that have been picked up for use in two new SSD families, replacing proprietary cores in their controllers: Mobiveil’s data centre centric FPGA-powered configurable storage family and Fadu’s more traditional Bravo family of enterprise SSDs.
 
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