Gowin Announces RISC-V Implementation Of Arora FPGA And An Alcom Electronics Distribution Tie-up In Europe

Gowin Semiconductor Corp., the leading programmable logic devices provider in China, today announces Industry Earlier Adopter Program of RISC-V microprocessor implementation of Gowin ARORA® Family, including FPGA programming bit-file of a system level reference design with RISC-V MCU core, AHB & APB Bus, Memory Control & Peripherals, as well as GW-2A development board as total solution.
RISC-V is an open specification of an Instruction Set Architecture (ISA). The RISC-V ISA has been designed with small, fast, and low-power real-world implementations in mind, but without over-architecting for a particular microarchitecture style. Gowin Arora® Family GW-2A FPGA are designed to offer the best-in-class performance cost ratio FPGA. With abundant logic, high performance DSP resources, and high speed I/O, the family is optimized for co-processing to offload the application processor on intensive computation tasks, as well as neatly optimized as the direct host of embedded microprocessor, like RISC-V ISA MCU soft core. The Arora® family is also the first FPGA with embedded SRAM in the industry, which gives customers more useable I/O. Gowin Industry Earlier Adopter Program of RISC-V Microprocessor offers a total solution.
 
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