UltraSoC Brings SEGGER J-Link To Embedded Debug And Analytics Environment

J-Link probes support RISC-V, Arm and other CPU platforms
UltraSoC today announced that it has partnered with SEGGER to offer support for J-Link debug probes within UltraSoC’s integrated system on chip (SoC) monitoring and analytics environment. SEGGER’s J-Link probes are amongst the industry’s most widely-used and support the debug of popular processor platforms including RISC-V, and both current and legacy Arm cores. The partnership gives SoC developers easy access to J-Link via a single interface when debugging using UltraSoC’s flexible on-chip monitoring and analytics infrastructure.
UltraSoC is dedicated to making designers’ lives easier: providing an open and accessible vendor-agnostic environment that suits the preferences of individual engineers in terms of processor architecture, development tools and hardware. In supporting the widest range of platforms and tools within its framework, UltraSoC opens the advantages of its embedded analytics platform to more designers, who benefit from faster development time, accelerated debug, and reduced risks and costs.
The integration of full support for SEGGER’s J-Link probes means that probe configuration and debug monitoring can take place under a single environment. In using UltraSoC’s embedded analytics, designers will get insights into the CPU’s operation, both during the design process and later in-field, as part of the wider system design.
 
To read more, please visit: https://www.ultrasoc.com/ultrasoc-brings-segger-j-link-embedded-debug-analytics-environment/