Esperanto, which is sponsoring the inaugural RISC-V Summit, will deliver a processor technology paper, and invites you to “Join the RISC-V Revolution!” to be part of the disruptive force transforming the microprocessor IP market through open standard collaboration.
Presentation: The Esperanto ET-Maxion™ High Performance Out-of-Order RISC-V Processor
This talk presents an update on ET-Maxion, a high frequency out-of-order RISC-V core which is being designed for TSMC’s 7nm process. It describes the key micro-architectural features that allow ET-Maxion to achieve performance levels comparable to existing commercial high-end processors, and discusses design choices, including shielding against timing attacks such as Spectre and Meltdown, with negligible performance sacrifices. Experiences in implementing the RISC-V compressed instructions (RVC) and the weak consistency model (RV-WMO) in a superscalar out-of-order core, along with design challenges, are shared. Finally, a brief overview of support for post-silicon debug and planned performance monitoring improvements for ET-Maxion.
To read more, please visit: https://www.esperanto.ai/single-post/2018/09/26/See-Esperanto-at-the-RISC-V-Summit-in-Silicon-Valley-December-2018.