Imperas has announced the RISC-V Open Virtual Platform Simulator (riscvOVPsim) as a reference Instruction Set Simulator (ISS), including open source model, specifically for the RISC-V community of software developers, implementers and early adopters. riscvOVPsim is a free RISC-V simulator and model of a complete single-core RISC-V CPU, delivering commercial high-level simulation performance and quality for development and compliance testing.The riscvOVPsim solution is an entry ramp for development, as well as a compliance testing tool.
For developers of more advanced RISC-V designs, who need multi-core support and advanced debug tools, Imperas also offers full-capability virtual platforms of some leading RISC-V platforms including the multi-core SiFive U540 and many others.
To read more, please visit: https://www.electronicsweekly.com/news/business/risc-v-open-virtual-platform-simulator-2018-11/.
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