SiFive released a new line of high performance RISC-V cores. The SiFive Core IP 7 Series provides a heterogenous, customizable architecture that allows the different cores in the series to be combined in a single coherent core complex. The E7 Series comprises 32-bit cores with hard real-time capabilities, S7 has a high performance 64-bit architecture for embedded markets, and U7 is a Linux-capable 64-bit applications processor with a configurable memory architecture for domain-specific customization.
RISC-V Summit: Dec. 3-6 in Santa Clara, CA. The first annual conference and exhibition dedicated to the RSIC-V ISA ecosystem. Training sessions, workshops, and presentations will be available, followed by a day for Foundation members.
To read more, please visit: https://semiengineering.com/the-week-in-review-design-138/.