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AnandTech Article: Western Digital Reveals SweRV RISC-V Core, Cache Coherency Over Ethernet Initiative

By December 5, 2018May 12th, 2021No Comments

Western Digital this week made three important announcements concerning its RISC-V-based processor initiative launched last year. The company introduced its own SweRV general-purpose core, its OmniXtend cache coherency over Ethernet technology, and the open-sourced SweRV Instruction Set Simulator (ISS). Western Digital expects that the hardware and software will be used for various solutions aimed at Big Data and Fast Data applications, including flash controllers and SSDs.
Western Digital’s RISC-V SweRV core is a 32-bit in-order core featuring a 2-way superscalar design and a nine-stage pipeline. When implemented using a 28 nm process technology, the core runs at up to 1.8 GHz. As for simulated performance, the SweRV core delivers 4.9 CoreMark/MHz. Western Digital will use its RISC-V cores for its own embedded designs, such as flash controllers and SSDs. The company will also make it available as an open-source product to third parties starting from Q1 2019. The company hopes that by enabling third-parties to use the core it will help to drive adoption of the RISC-V architecture by hardware and software developers eventually.
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