I titled my preview of the RISC-V Summit RISC-V Summit Preview: Pascal or Linux? Since it is clear that RISC-V is really the only game in town inside academia, but it still hasn’t conquered the commercial world. So it’s already Pascal but not Linux.
Some Highlights of the Summit
It is still too soon to say, but here are a few datapoints that I will either cover in more detail below or in future posts.
- Western Digital (plus Sandisk inside) announced last year that they would use RISC-V for all their processors. This year, they announced SweRV, which is a dual-issue in-order processor with impressively high performance. They also announced that they would completely open source it, along with some other pieces of RISC-V ecosystem.
- Qualcomm‘s presentation: “I end with an announcement: Qualcomm will be shipping RISC-V in a high volume product in 2019.”
- Google announced an UVM-based RISC-V verification platform that they will open-source.
- FADU announced the first shipping datacenter storage controller based on RISC-V with impressive performance/power numbers.
- SiFive sponsored the Linus Tech Tips Video #1 on RISC-V. It has 2.5M views on YouTube, Guancha, WeChat, Youku, CNX. They also (at Linley recently) announced a whole range of cores.
- During the summit, NXP gave away 700 Vega boards with Arm, RISC-V, and a lot of wireless cores on a single SoC. See picture of mine on the right.
- Esperanto gave details of their out-of-order RISC-V core, Maxion (that goes with their AI core Minion) including performance details. It will tapeout early next year. This is the highest performance RISC-V core that has been disclosed.
- Commercial core providers: Andes, Bluespec, Cloudbear, Codasip, Cortus, C-Sky, Nuclei, SiFive, Syntacore. Krste: “Never been a single ISA with this many commercial providers.”
- Rick O’Connor, who runs the RISC-V Consortium, said that the question he gets asked all the time is whether anyone is actually shipping parts in volume. He said that in 2019, to give you an idea, there will be more than 10 million but less than 100 million chips containing RISC-V processors. There are 200 members in the foundation (see chart below). There were twice as many people (over 1000) at the RISC-V Summit as attended the equivalent workshop in 2017.
To read more, please visit: https://community.cadence.com/cadence_blogs_8/b/breakfast-bytes/posts/riscv18.