EET China Article: How Is The Commercial Situation Of Each RISC-V Product?

The RISC-V camp announced at the first Open Source Instruction Set Architecture (ISA) annual summit held earlier this month that RISC-V is officially “open”! The event, which was held in Silicon Valley, debuted in the industry’s many core, FPGA, artificial intelligence (AI) and interconnect chips that will be commercially available. This is also the time when China is actively reorganizing up to hundreds of RISCs for the architecture. RISC-V core and dozens of cores in development.
In this event, Western Digital (WD) detailed a 32-bit embedded core planned for use in consumer solid-state drive (SSD) controllers shipped in 2020. In addition to the open source core, WD also introduced a cache coherent interconnect protocol for RISC-V processors. In addition, the company has also started 64-bit core development work.
 
To read more, please visit: https://www.eet-china.com/news/201812220754.html.Please note that the original article is in Chinese.