EETimes Article: RISC-V Takes A Leap Forward

RISC-V is open for business, proponents will claim at the first annual summit for the open-source instruction set architecture today. The Silicon Valley event comes at a time when backers say that China is rallying around the architecture with perhaps hundreds of RISC-V SoCs and dozens of cores in the works.
At the event, Western Digital will detail a 32-bit embedded core that it will use in a controller for a consumer solid-state drive set to ship in 2020. It is releasing as open-source both the core and a protocol for a cache-coherent interconnect for RISC-V processors — and it has started work on a 64-bit core.
The Microsemi division of Microchip will describe a five-core complex that it will embed in its PolarFire FPGAs by early 2020. The chip marks its first step in a plan to standardize on use of RISC-V.
In the hot field of machine learning, startup SiFive will describe two RISC-V chips — an embedded inference device based on Nvidia’s Deep Learning Accelerator and a training chip using newly mined RISC-V vector extensions along with HBM2 memory and 56-Gbit/s SerDes.
Separately, Google, an early member of the RISC-V Foundation, will show its TensorFlow Lite software geared for embedded systems running on the Zephyr operating system on a RISC-V chip. For its part, Bitmain, a leader in bitcoin-mining silicon, will reveal that its Sophon Edge AI chip announced last year uses a RISC-V core as its sensor hub.
 
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