This blog will look at recent developments in RISC-V and in particular at announcements by Western Digital at the 2018 RISC-V Summit in Santa Clara, CA. RISC-V is an open, scalable instruction set architecture. RISC-V is descended from the original RISC computing architecture from the 1980s.
Proponents of RISC-V say that it that enables the diversity of Big Data and Fast Data applications and workloads proliferating in core data centers and in remote and mobile systems at the edge. It provides an alternative to current, standard, general purpose compute architectures. With RISC-V, open standard interfaces can be utilized to enable specialty processing, memory centric solutions, unique storage and flexible interconnect applications. The RISC-V Foundation has a broad ecosystem represented by the significant increase in attendees at the 2018 Summit compared to 2017.
At the RISC-V summit, Western Digital announced three new open-source innovations designed to support Western Digital’s internal RISC-V development efforts and those of the growing RISC-V ecosystem. In his keynote address, Western Digital’s Chief Technology Officer Martin Fink unveiled plans to release a new open source RISC-V core (SweRV), an open standard initiative for cache coherent memory over a network (OmniXtend) and an open source RISC-V instruction set simulator (SweRV ISS). These innovations are expected to accelerate development of new open, purpose-built compute architectures for Big Data and Fast Data environments.
To read more, please visit: https://www.forbes.com/sites/tomcoughlin/2018/12/10/western-digital-takes-a-risc/#7cda00702bb5.