TechRepublic Article: Western Digital Will Open Source SweRV RISC-V CPU Designs And Tools

On Tuesday, Western Digital, an early adopter and vocal proponent of RISC-V, announced plans to open source their implementation of the RISC-V ISA and associated development resources, providing the ability for the open source community to utilize their implementation of the architecture in their own products as well as iterate on it to meet the needs of their own products.
SweRV Core EHX1, the first generation of RISC-V processors at Western Digital, is a 32-bit, 2-way superscalar, 9 stage pipeline core capable of clock speeds up to 1.8 GHz, produced on a 28mm CMOS process, at 4.90 CoreMark/MHz. For their own products, Western Digital touts it as being fit for “embedded devices supporting data-intensive edge applications, such as storage controllers, industrial IoT, real-time analytics in surveillance systems, and other smart systems.” Plans for SweRV Core will be released in Q1 2019.
 
To read more, please visit: https://www.techrepublic.com/article/western-digital-will-open-source-swerv-risc-v-cpu-designs-and-tools/.