UltraSoC Blog Post: RISC-V Summit: Automotive Developments, System-Level Design, WD SweRV Core, And More…

The first RISC-V Summit, which took place in Santa Clara, CA early this month, looks likely to be a watershed for the RISC-V ecosystem.
The technology is maturing and the ecosystem is growing fast – and that was reflected in the nature of the presentations and news announcements we saw. The accent has started to move to how the technology will be used in real life: UltraSoC’s announcement of a hardware-basedlockstep solution for automotive applications being a good example. RISC-V lacks native support for lockstep, which is strongly recommended for designs with a functional safety dimension.
Meanwhile at the conference, our CTO Gajinder Panesar continued to encourage ecosystem members to take a more system-level approach, as well as pushing forward the ISA and core design dimensions. Gadge argues that RISC-V will take its place alongside a raft of other processor architectures – most notably Arm. So developing an ecosystem that can support heterogeneous designs – those that include cores built with different base architectures – is vital.
 
To read more, please visit: https://www.ultrasoc.com/risc-v-summit_automotive_system-level-design_wd-swerv-core/