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UltraSoC Blog Post: Systemic Complexity: Time For RISC-V To Rise To The Challenge

By December 5, 2018May 12th, 2021No Comments

As we gather here in Santa Clara for the 2018 RISC-V Summit, I’m excited to learn about new developments in the ecosystem, and the progress that’s been made since the last major RISC-V Foundation event in Barcelona back in May.

But as we look forward to a bright future for RISC-V, it’s important to focus on what really matters. For chip architects and designers today, “the ISA” is a small consideration. The concern isn’t even choosing “the core”. Designers today are faced by a “whole system” problem: a problem of systemic complexity.

That fact is implicit in the picture that I show people to explain the UltraSoC embedded analytics architecture. It shows a block-level representation of an SoC, with a broad range of compute nodes, memory and custom logic, interconnected by a NoC. One of those compute blocks is a RISC-V processor. It’s an important component. But it’s one amongst many. RISC-V is going to be used alongside other architectures for the foreseeable future, and probably forever.
Everything will change: but we’re not faced with a binary choice.
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