AB Open Article: CRU: Raspberry Pi Goes RISC-V, New FOSS Business Model, KiCon 2019, And More

Thales, which recently became a member of the RISC-V Foundation, has announced a joint project with IIT Madras to develop a fault-tolerant version of the SHAKTI Project RISC-V CPU.
“After the two successful fabrication and booting of SHAKTI with two technology nodes, 22nm (Intel Fab, Oregon USA) and 180nm (SCL Chandigarh fab, India), this tie-up with Thales is very exciting and certainly is a big step towards taking SHAKTI family to the global technology ecosystem,” claims Professor Kamakoti Veezhinathan of the Reconfigurable Intelligent Systems Engineering (RISE) Laboratory at IIT Madras. “With the advent of more and more safety critical systems adopting electronics hardware for intricate control and monitoring, fault-tolerance and security features are of prime importance in next generation processors. This tie-up with Thales, I am sure, will result in a detailed analysis of these features resulting in a framework that could be adopted for designing the next generation Shakti-based safety-critical systems.”
RISC-V specialist Bluespec Inc. has announced its second RISC-V processor design, Flute, which it is making available as basic cores ahead of future releases which will include additional instructions for Linux and FreeRTOS compatibility.
The follow-up to Bluespec’s existing Piccolo core, Flute is currently available in RV32IMU and RV64IMASU implementations with a floating-point and compressed-instruction variant supporting Linux and FreeRTOS operating systems to follow. The core uses a five-stage pipeline, can run at 100MHz on the Xilinx UltraScale field-programmable gate array (FPGA) platform using fewer than 5,000 look-up tables (LUTs), with 4KB instruction and data cashes and hardware multiply-divide.
 
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