Andes Technology Video: The Promises And Pitfalls Of RISC-V, From SoC Design Perspective (D&R IP SoC Day Panel)

On Thursday, April 5, 2018, Design&Reuse hosted the D&R IP SoC day at the Hyatt Hotel Santa Clara. Presenting at panel, “The Promises And Pitfalls Of RISC-V, From SoC Design Perspective,” Emerson Hsiao of Andes Technology USA Corp. joins Art Swift of Esperanto Technologies, Inc., Ted Speers of Microsemi Corp. and Naveed Sherwani, SiFive, Inc. to discuss the advantages and disadvantages of RISC-V for chip design.
 
To read more, please visit: https://www.youtube.com/watch?v=68y_WoqP6LY.