UltraSoC has extended its on-chip analytics architecture to provide monitoring and analytics of complex machine learning (ML), artificial intelligence (AI), and parallel computing chips comprising up to 65,536 elements.
The new architecture, to be introduced in the company’s UltraDevelop 2 integrated development environment (IDE), allows system-on-chip (SoC) designers to build on-chip monitoring and analytics systems with up to 65,536 elements, allowing seamless support for systems with many thousands of processors. This makes it suitable for monitoring a massive number of the internal building blocks that make up the most complex SoC products — and analyzing the impact on system-level behavior of the interactions between them.
UltraSoC CEO Rupert Baines said, “Our solutions are unique in the market in their ability to deal with multiple heterogeneous processors, standard and proprietary bus structures, and even custom logic. This dramatic extension of our architecture takes us even further ahead of traditional solutions, both in the debug and development arena, and in allowing our customers to incorporate in-life monitoring capabilities to ensure security, functional safety, and real-world performance optimization.”
Dave Ditzel, founder and CEO of Esperanto, developer of energy-efficient high-performance computing systems for ML and AI applications, said that with their products incorporating over a thousand RISC-V processors and AI/ML accelerators on a single chip, UltraSoC’s ability to match that level of scaling with monitoring, analytics, and debug capabilities is a vital enabler for its business. Esperanto is the lead customer for its solution at present, with a system that has 4,000 cores with one architecture and 64 cores with another, all based on RISC-V.
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