The RISC-V Foundation believes their solution has paved the way for the next 50 years of computing design and innovation, and it’s easy to see why: RISC-V’s open set instruction architecture ensures a future of more extensible, long-lasting hardware. Western Digital’s Ted Marena, director of RISC-V’s ecosystem, talked to Electronics Point about his background and knowledge of the platform.
Having started his career as a design engineer for Wang Computers, it was after around four years that Ted Marena found his energetic personality was well suited to more outgoing positions, and eventually took on field applications engineering before later finding a new niche in sales management.
This then led to a more marketing-based background for Marena, and it was whilst he was working as a director of outbound marketing for Microsemi’s SOC and FPGA business unit that he and his department started to look at a RISC-V (pronounced ‘risk-5’) workshop for customer solutions.
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