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Elektronik Article: Open Source Hardware RISC-V The Way To Industrial Application

By February 19, 2019May 12th, 2021No Comments

The RISC-V instruction set architecture must be carried out of the academic circle of colleges into the industry in applications to be successful. Prof. Robert Oshana from NXP Semiconductors knows how practical entry can be made for companies.

The move from research to industrial application can be an obstacle that should not be underestimated. In particular, industrial companies face the challenge of adapting to existing, established processes and quality standards.
A practical approach to implementing the open instruction set architecture RISC-V has been developed by Prof. Robert Oshana, who is Vice President of Software Research and Development for the microcontroller and microprocessor business of NXP Semiconductors. He will also speak at the embedded world Conference 2019 . He opened Session 5 “RISC-V” on 26 February 2019 with his presentation “RISC-V Practical Industry Approach to Getting Started with This Technology”.
Prof. Oshana, what is the biggest challenge for companies and developers who want to develop a SoC with RISC-V for the first time?
Robert Oshana: In many ways, the implementation of a RISC-V core is similar to the process of implementing a different hardware IP.

  • You want to make sure you have the right verification coverage for the IP.
  • You want to make sure you have adequate software support for the IP.
  • And you want to make sure you have the right tools to support the IP.

If you go to a commercial RISC V provider, you can find all of this. If you want to use a community RISC V kernel such as PULPino, you may need to do extra work to get the necessary core software and tools. If you plan to extend the instruction set, you should have a plan to support the command extensions as well as to test and verify these extensions.
Therefore, it is helpful to use a suitable emulation / FPGA environment for this analysis. When using a RISC V core for the first time, it may be necessary to develop some additional assistive IPs for customization and interlayers, so that the core can be easily integrated into the SoC and fewer changes need to be made to the existing verification environment.

To read more, please visit: Please note that the original article is in German.

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