ExtremeTech Article: Western Digital’s RISC-V ‘Swerv’ Core Now Available For Free

Western Digital has announced that it’s completed work on its Swerv RISC-V CPU core and has published the register-transfer level (RTL) abstraction of the design. Publishing the RTL code allows other companies to use the design.
Open-source hardware initiatives and ISAs have existed for decades, but RISC-V has gathered a critical ecosystem and corporate interests in these projects where historically there was little incentive to buy-in. The issue isn’t primarily cost savings — particularly as node sizes decrease, the licensing costs of an ARM core simply aren’t a major part of the total. The end of conventional Moore’s Law scaling has moved interest back to ISAs, as has the rise of IoT, AI, ML, and the need for new architectures to address these challenges.
 
To read more, please visit: https://www.extremetech.com/computing/285856-western-digitals-risc-v-swerv-core-now-available-for-free.