Media Alert: RISC-V Comes To DVCon

WHO: The 2019 Design and Verification Conference and Exhibition (DVCon) U.S.
WHAT: Will include “Verification and Compliance in the Era of Open ISA –– Is the Industry Ready to Address the Coming Tsunami of Innovation?,” a panel exploring the RISC-V instruction set architecture’s features, benefits and challenges for processor IP and SoC development.
WHEN: Wednesday, February 27, from 8:30 a.m. until 9:30 a.m.
WHERE: Oak/Fir Room, DoubleTree Hotel, San Jose, Calif.
Moderator Kevin Krewell, principal analyst at TIRIAS Research, will lead panelists in a discussion about the RISC-V open standard, including the dynamic of compliance and customization, and defining requirements for identifying restrictions to customization.
 
To read more, please visit: https://globenewswire.com/news-release/2019/02/21/1739951/0/en/MEDIA-ALERT-RISC-V-Comes-to-DVCon.html.