https://riscv.org/).
Like most modern ISAs, it is based on reduced instruction set computing (RISC) principles that provide a good balance between silicon footprint, execution speed and code efficiency. The instruction set can be instantiated with a 32-, 64-, or 128-bit word width and has been designed to efficiently support a wide variety of common applications. Unlike proprietary ISAs, the RISC-V ISA may be freely used for any purpose, enabling anyone to design, produce or sell RISC-V chips and software.
To read more, please visit: https://opensourceforu.com/2019/02/how-open-source-technologies-accelerate-innovation/.]]>