Semiconductor Engineering Article: Week In Review: Design, Low Power

OneSpin unveiled a set of formal apps for development and assessment of RISC-V cores. The RISC-V Integrity Verification Solution formalizes the RISC-V ISA in a set of SystemVerilog Assertions to verify compliance for the ISA is met. It provides a formal bug absence core assessment environment for unbounded proofs and systematic discovery of all hidden instructions or unintended side effects and also verifies that cores do not contain hardware Trojans or other unintended functionality.
UltraSoC announced its embedded analytics architecture fully supports Western Digital’s RISC-V SweRV Core and associated OmniXtend cache-coherent interconnect. The debug and on-chip analytics ecosystem will support the requirements of both Western Digital’s internal development teams and third parties choosing to adopt the SweRV Core for their own applications. SweRV is intended for development of open, purpose-built compute architectures for Big Data and Fast Data environments.
 
To read more, please visit: https://semiengineering.com/week-in-review-design-low-power-31/.