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Codasip To Demonstrate Technology Leadership And Commitment To Open Standards At Taiwan RISC-V Workshop

By March 7, 2019May 12th, 2021No Comments

Codasip GmbH, the leading supplier of configurable RISC-V embedded processor IP, will address the topics of RISC-V C compiler optimizations and frameworks for ISA compliance in two presentations at the upcoming RISC-V Workshop in Taiwan.
In the first presentation, Codasip CTO Zdeněk Přikryl will demonstrate how Codasip generates and optimizes the latest LLVM version 7.0.1 toolchain to make use of custom instructions, including debugging and profiling. The LLVM project continues to expand rapidly as industry leaders have chosen to adopt LLVM compiler due to its excellent quality of results. While many employ various components of the LLVM toolchain, Codasip has announced availability of LLVM for compilation, code generation, and debugging for its family of RISC-V processors. Full support for LLDB in command-line mode or as part of an Eclipse-based graphical debug is now part of its latest generation of licensable software development tools.
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