PULP – Parallel Ultra-Low-Power Processing-Platform, is a research programme between the Integrated Systems Laboratory (IIS) of ETH Zurich and the Energy-Efficient Embedded Systems (EEES) group of University of Bologna – towards an open, scalable hardware and software research platform that will achieve the highest possible energy efficiency (goal is to “break pJ/op barrier”) within a power envelope of a few mW – according to ETH.
OpenMP, OpenCL and OpenVX are supported on PULP. PULP features, from project page
- Implementations of RISC-V cores, including
32bit 4-stage core RI5CY
32bit 2-stage Zero-riscy and Micro-riscy
64bit 6-stage Ariane