Andes Technology unveiled its 32-bit A25MP and 64-bit AX25MP RISC-V multicore processors with comprehensive DSP instruction extension. Both support up to four CPU cores and operate at over 1GHz in 28nm process with Linux symmetric multiprocessing (SMP) support. They provide efficient cache coherence among private level-1 caches; include an optional shared level-2 cache; and support I/O coherence for bus masters without caches.
To read more, please visit: https://semiengineering.com/week-in-review-design-low-power-34/.
Stay Connected With RISC-V
We send occasional news about RISC-V technical progress, news, and events.
Copyright © 2023 RISC-V International®. All rights reserved. RISC-V, RISC-V International, and the RISC-V logos are trademarks of RISC-V International. For trademark usage guidelines, please see our Brand Guidelines and Privacy Policy