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Decreasing The Length Of Design Cycle In Co-Designed SoCs With Renode

By April 16, 2019May 12th, 2021No Comments

In this article, we explain how the use of open-source functional simulators like Antmicro’s Renode can be an integral part of hardware-software co-design efforts.
As markets demand more from their embedded systems, next-generation SoCs are becoming more complex, leading to lengthier design cycles and rising costs, according to Semico Research.
The frustrating reality for device makers is that the only way to deliver the new and innovative features, greater security, and better performance that their customers are asking for, is to engage in “whole stack” co-design, evolving hardware, firmware, runtime (OS), and development toolchain in tandem. Doing so allows hardware and software teams to address complex tradeoffs around where in the stack to implement functionality and optimizations.
The hardware team at Dover uses a standard SystemVerilog-based process and toolchain. Initial prototypes of the CoreGuard system are built on RISC-V based SoCs. Because CoreGuard has a substantial software component in addition to the hardware IP, it was important that the software team be able to start well before any hardware prototypes were available.
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