OneSpin Solutions unveiled a formal RISC-V Verification App. The app is intended to exhaustively verify that RISC-V cores are developed and integrated with zero bug escapes and guarantee full compliance with the ISA, even with the range of configuration options available. OneSpin says the automated solution needs only a few days to set up and only two hours to run on a complete core. In addition, OneSpin’s 360 EC-FPGA now supports three Intel FPGA families, Stratix 10, Arria 10, and Cyclone V using Intel Quartus software for synthesis and place-and-route. The company says the move to support FPGAs used in high-bandwidth applications meets demand from verification engineers for formal equivalence checking solutions that ensure functional correctness of FPGA designs. The tool is implemented in the FPGA flow from RTL to place-and-route to check RTL code against a post-synthesis, gate-level netlist. To read more, please visit: https://semiengineering.com/week-in-review-design-low-power-44/]]>