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Andes Technology Announces Coming Up The North America Annual RISC-V CON 2019 Santa Clara | Andes Technology (Press Release)

By September 26, 2019May 12th, 2021No Comments

Santa Clara, US – September 24, 2019 – The RISC-V CON 2019 held in Santa Clara on October 15 will feature the first independent analysis of the commercial potential for the open source architecture RISC-V market opportunity. Jim Feldhan, President of Semico Research will present the findings of his firm’s evaluation based on research commissioned by the RISC-V Foundation. Amazon will provide a RISC-V user’s perspective in a technical presentation detailing an AI compiler based on RISC-V. Imperas will release their next generation software tools for developing RISC-V based SoCs. Faraday will offer a design service’s viewpoint on building a RISC-V based ASIC solution for edge AI and IoT SoC.
Andes Technology CTO and Executive VP Charlie Su, will present “Powering RISC-V SoCs with 1 to 1,000s AndesCores.” His presentation will illustrate the range and versatility of the RISC V instruction set architecture (ISA) that is propelling the ISA’s widespread adoption by everyone from start-ups to Fortune 500 companies in applications spanning Internet of Things to multiprocessor AI devices. To conclude up the seminar, a panel moderated by Jim Feldhan will discuss how Andes, Amazon, Imperas and Faraday are driving RISC-V adoption.
During RISC-V CON, presentations, partner exhibitions and live demo will enable attendees to learn more about the advanced RISC-V ISA technology. Through face-to-face interactions with RISC-V ecosystems and partners, attendees will get more latest, leading-edge information on this rapidly emerging new CPU architecture. For more information about RISC-V CON, please visit

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