SAN MATEO, Calif. – September 23rd, 2019 – SiFive, Inc., has announced the general availability of the latest update to SiFive Core IP and SiFive Core Designer in the Q3 2019 quarterly update. This release is specifically focused on the enablement of Trace and Debug functionality in the development of configurable SoC design.
Real-time analysis enabled via tracing permits a deeper insight into the interactions of software and hardware to accelerate development, debug, and validation. To support this goal, the full range of SiFive Core IP is now enabled with Nexus 5001™ Instruction Trace capabilities.
article: https://www.sifive.com/press/sifive-announces-key-enablement-of-trace-and-debug
Stay Connected With RISC-V
We send occasional news about RISC-V technical progress, news, and events.
Copyright © 2023 RISC-V International®. All rights reserved. RISC-V, RISC-V International, and the RISC-V logos are trademarks of RISC-V International. For trademark usage guidelines, please see our Brand Guidelines and Privacy Policy