Why RISC-V Will Prevail | Marc Sauter, Golem

At lunch at the RISC-V workshop in Zurich, Krste Asanovic succinctly answers the initial question: “RISC-V is called that because it is our fifth major RISC architecture.” Asanovic must know, because the Berkeley University professor is co-inventor of the Open CPU (Open Hardware ISA) architecture. It was designed in 2010 together with RISC veteran David Petterson and made available in 2014.
article (in German / auf Deutsch): https://www.golem.de/news/offene-prozessor-isa-wieso-risc-v-sich-durchsetzen-wird-1910-141978.html