SystemVerilog linting and formatting with FuseSoC – Verible integration | Antmicro

Although new ASIC design methodologies and tools such as Chisel are on the rise, most ASIC projects still use SystemVerilog, the support of which in open source tools has traditionally lagged behind. This is unfortunate, as using proprietary alternatives with the CI systems of open source projects is neither scalable due to licensing costs and restrictions nor simple due to the need for license management and obfuscation.
Antmicro, Google and the CHIPS Alliance, which we are members of, have been working together with the lowRISC project to address this issue by implementing relevant tools and useful integrations in the open source domain. One large milestone on this route is Verible, an open source Flex/YACC SystemVerilog parser, linter and formatter recently open sourced by our partner and customer, Google.
article: https://antmicro.com/blog/2020/04/systemverilog-linter-and-formatter-in-fusesoc/