Andes Plots RISC-V Vector Heading | Mike Demler, The Linley Group

RISC-V International, formerly the RISC-V Foundation, expects to release its v1.0 vector-extension (RVV) specifications in August. But Andes has already delivered the first CPU core to support the new features. The NX27V is a 64-bit design that implements the RISC-V RV64 ISA, RVV, and proprietary Andes extensions. The scalar processing unit employs the same architecture as the company’s NX25: a single-issue five-stage microcontroller CPU. The new vector processing unit (VPU) adds configuration options for 128-, 256-, and 512-bit SIMD operations. Andes recently delivered production RTL to its lead customer, which is using it in a 7nm design. The NX27V should be available for general licensing in October.
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