The RISC-V opportunity for FPGA | Jim Hogan, Vista Ventures LLC

by Jim Hogan, Vista Ventures LLC, Santa Cruz, CA.
Sheltering in place has given me time to consider the world around me. I work as an investor in technology and specifically spend a great deal of time in startups that are looking at IoT edge-based semiconductor devices. Many of these companies are using or considering using RISC-V solutions for their processing needs. In my world there is a definite trend toward RISC-V and I thought it might help others if I shared some thoughts.
RISC-V is an open Instruction Set Architecture (ISA) started at UC Berkeley in 2010 , one of the primary inventors of RISC technology. There has never been an open ISA with the freedom of use and engineering excellence RISC-V provides. This approach put it on the fast track to become the first open source ISA with broad industry support. High-profile corporate leaders like Western Digital, NXP, Google, Nvidia and Microsemi are supporting the RISC-V Foundation, CHIPS Alliance and the OpenHW Group to maintain the ISA, build the ecosystem and develop open source cores. It has legs and real momentum in my opinion.
RISC-V is taking off much more quickly than I had ever expected it to. I think it will result in a big opportunity for FPGAs to encroach even more on ASICs and ASSPs. In my recent experience most SoCs pass through an FPGA on the way to ASIC, starting with validation using FPGA-based emulation or prototyping. And many SoC projects start shipping as FPGA while the ASIC is being developed. This is the case with several startups I’m invested in now. RISC-V can help FPGAs incentivize delaying and even canceling plans to develop an ASIC. Ironically, greasing the path from FPGA to ASIC is an opportunity to grow FPGA revenues.
Another way to look at the FPGA opportunity is to consider the $130M + investment in SiFive to build a new-age fabless ASIC company based on an accelerated concept-to-silicon strategy. While SiFive is attacking the strategy with much energy and talent, they must envy FPGA companies with their installed concept-to-silicon platforms and thousands of customers moving into silicon on their own. It feels like a huge missed market and revenue opportunity that FPGA companies are not making the modest investment to enhance their platforms with RISC-V (Microsemi made the only serious effort with its RISC-V based configurable SoC).
The good news for FPGA companies is that the ecosystem work is increasingly being done by the RISC-V open source community. The heavy lifting of developing the ISA, toolchain and software stack no longer falls on a single company. The only remaining step needed to plug FPGAs into the RISC-V ecosystem are RISC-V cores productized for FPGA and migratable to ASIC.

RISC-V will change the embedded processor landscape as we know it

Next generation SoCs will rely heavily on customized processors to implement domain-specific architectures (DSAs) to achieve the performance and power improvements that Moore’s law can no longer provide. Tier 1 companies like Apple, Qualcomm, and Samsung have been doing this for years with large design teams and expensive architectural licenses that allow them to customize ARM processors. Others roll their own hardware accelerators or add custom instructions to affordable processor cores like ARC and Tensilica.
For many of the edge-based devices, ARM customization is not an economical mainstream option. ARC and Tensilica are proprietary ISAs that will prevent them from scaling to an industry wide processor platform now that the RISC-V cat is out of the box.
RISC-V has become a top choice for innovators. It is inherently low power – having started with a clean slate, it can be implemented with a minimal set of instructions that avoids the bloat of legacy ISAs. It was developed with architectural innovation in mind – supporting 16-bit to 128-bit instructions, custom extensions, multi-core, many-core and hardware acceleration – and it’s become the number one ISA for developing hardware based cybersecurity systems.
ARM’s market dominance is assured for years to come by legacy software and its monopoly in mobile. However, the open source RISC-V innovation wave will change the rest of the embedded processor landscape as we know it:

• Mass collaboration will build the RISC-V ecosystem to a level that obsoletes proprietary ISAs
• MIPS, ARC, Tensilica, MicroBlaze, Nios will all fade away
• The primary innovation vehicles will be RISC-V and FPGA
• The new wave of innovation will flow to FPGA companies with the best RISC-V support

RISC-V has what it takes to be an ASIC processor platform. The increasingly robust RISC-V ecosystem work has been done by the RISC-V open source community. It’s worth repeating – the heavy lifting of developing the ISA, toolchain and software stack no longer falls on a single company. The only thing needed to plug FPGAs into the RISC-V ecosystem are RISC-V cores productized for FPGA and migratable to ASIC.

The FPGA opportunity and MCUs

I said earlier that RISC-V can help FPGAs incentivize delaying and even canceling plans to develop an ASIC, and ironically, greasing the path from FPGA to ASIC is an opportunity to grow FPGA revenues. Let’s look at a simple example.
The opportunities to change course on the path to ASIC are multiplying as FPGAs integrate more and more hard cores for standard components like Ethernet, USB, PCIE, DDR and multi-core processor subsystems. And new application workloads that require architecture and memory optimization over frequency are making SoC performance less sensitive to the lower speed of programmable logic. Surprisingly, the new math suggests that even MCUs (microcontrollers) – standard off-the-shelf ASIC SoCs – are open to encroachment by FPGAs running processor soft cores.
At the high end of MCUs (32/64-bit processors, GHz frequencies), new workloads requiring DSAs will eliminate general-purpose MCUs as an option. The next option is a configurable SoC (cSoC) – an MCU with FPGA programmable logic. If the DSA maps into a cSoC and meets the performance, power and cost constraints, the SoC moves from MCU to cSoC.
If not, the next option is to spin an ASIC, which will start with an FPGA prototype or emulation, because the only sure way to validate architectural performance is to run the application code on the hardware. In the process, an unanticipated option might be a generic FPGA with a processor soft core delivering good enough performance. If the generic FPGA meets the product’s power and cost requirements, the socket moves from MCU to a generic FPGA with a soft-core processor.
You can see how the numbers could work out in the table below, where a generic FPGA with a processor soft core provides good enough performance using a solution with much lower cost and complexity (scenario illustrates an application for which an MCU must be replaced by a DSA with a hardware accelerator that offloads 90% of the work from the general-purpose processor and executes it 10x faster):
ASIC custom

At the low end (16-bit processors, <100 MHz) the market is driving the integration of MCUs, FPGAs and other board chips to improve performance, power and cost. FPGA suppliers responded a decade ago with cSoCs, and while many MCUs made the transition, many others did not due to cost or lack of system fit. These remaining MCU sockets will lose market share to the new degrees of freedom offered by inexpensive FPGAs and RISC-V soft cores.

Conclusions

It is inevitable that in the near future FPGAs with RISC-V cores will be the innovation platform for the next generation of IoT edge-based devices. These designs will start with FPGA-based prototyping and emulation. In the process many systems will find that an FPGA RISC-V based solution provides good enough performance, power, and cost. I think it is just a matter of time until all FPGA suppliers have a RSIC-V softcore offering. This will benefit both the systems customers as well as the FPGA manufacturers themselves.
And while we are talking about change, it is also very likely that we’ll see significant use of the cloud for RISC-V based innovation. FPGA-based emulation provides a big cost savings over traditional emulators, but not everyone takes advantage of this because it’s complicated. Having a simplified IoT device emulation capability in the cloud – like how AWS-FPGA simplifies data center acceleration – could be a real game changer.
Please let me know your opinion. Thanks