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Aldec Provides Static Verification for RISC-V Designs with the Latest Release of ALINT-PRO

By July 23, 2020April 28th, 2021No Comments

Henderson, NV, USA – July 22, 2020 – Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has added a RISC-V focused static verification rule set to ALINT-PRO™; rules that statically validate HDL code quality prior to simulation.
Based on industry best-practice coding techniques and Aldec’s 36 years of verification experience, the new RISC-V rule set helps designers statically verify home-grown RISC-V designs, as well as helping IP integrators select and properly integrate open-source RISC-V cores into their SoCs.

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