Imperas RISC-V reference simulator and model extended for coverage analysis

By RISC-V Community NewsOctober 15, 2020November 2nd, 2020No Comments

Imperas RISC-V reference simulator and model extended for coverage analysis, plus test suite for latest RISC-V Vector Instruction Extensions.

riscvOVPsim™ updated for the latest RISC-V Vector Instructions Specification, for coverage-based DV methodologies with Verification IP for architectural validation.

Read the full press release.

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Imperas RISC-V reference simulator and model extended for coverage analysis

Previous PostSiFive/RISC-V Questions w/James Prior

Next PostRISC-V: Will There Be Other Open-Source Cores? | Ed Sperling, Semiconductor Engineering

Stay Connected With RISC-V