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Imperas Extends free riscvOVPsimPlus Simulator for RISC-V | Imperas

riscvOVPsimPlus™ includes latest reference model and now offers expanded simulation features for debug & trace for early software development and hardware verification.

Oxford, UK – December 4th, 2020 – Imperas Software Ltd., the leader in RISC-V processor verification solutions, today announced that the Free riscvOVPsimPlus™ RISC-V reference model and simulator, which has been widely adopted across the RISC-V ecosystem, has been updated and extended with additional features including full configurable instruction trace, GDB/Eclipse debug support, plus memory configuration options. Additionally, included in the updated model are the full standard CLIC features, Debug Module / Mode, Hypervisor “H” simulation, and also ‘near-ratified’ ISA extensions for Vector “V”, Bit Manipulation “B”, and Crypto (Scalar) “K” extensions.

Read the full press release.

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